Device and method for scalable coding of video information

ABSTRACT

An apparatus configured to code video information includes a memory unit and a processor in communication with the memory unit. The memory unit is configured to store video information associated with a reference layer (RL) and an enhancement layer (EL), the RL having an RL picture in a first access unit, and the EL having a first EL picture in the first access unit, wherein the first EL picture is associated with a first set of parameters. The processor is configured to determine whether the first EL picture is an intra random access point (IRAP) picture, determine whether the first access unit immediately follows a splice point where first video information is joined with second video information including the first EL picture, and perform, based on the determination of whether the first EL picture is an intra random access point (IRAP) picture and whether the first access unit immediately follows a splice point, one of (1) refraining from associating the first EL picture with a second set of parameters that is different from the first set of parameters, or (2) associating the first EL picture with a second set of parameters that is different from the first set of parameters. The processor may encode or decode the video information.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to U.S. Provisional No. 61/891,264, filed Oct. 15, 2013.

TECHNICAL FIELD

This disclosure relates to the field of video coding and compression, particularly to scalable video coding (SVC), multiview video coding (MVC), or 3D video coding (3DV).

BACKGROUND

Digital video capabilities can be incorporated into a wide range of devices, including digital televisions, digital direct broadcast systems, wireless broadcast systems, personal digital assistants (PDAs), laptop or desktop computers, digital cameras, digital recording devices, digital media players, video gaming devices, video game consoles, cellular or satellite radio telephones, video teleconferencing devices, and the like. Digital video devices implement video compression techniques, such as those described in the standards defined by MPEG-2, MPEG-4, ITU-T H.263, ITU-T H.264/MPEG-4, Part 10, Advanced Video Coding (AVC), the High Efficiency Video Coding (HEVC) standard presently under development, and extensions of such standards. The video devices may transmit, receive, encode, decode, and/or store digital video information more efficiently by implementing such video coding techniques.

Video compression techniques perform spatial (intra-picture) prediction and/or temporal (inter-picture) prediction to reduce or remove redundancy inherent in video sequences. For block-based video coding, a video slice (e.g., a video frame, a portion of a video frame, etc.) may be partitioned into video blocks, which may also be referred to as treeblocks, coding units (CUs) and/or coding nodes. Video blocks in an intra-coded (I) slice of a picture are encoded using spatial prediction with respect to reference samples in neighboring blocks in the same picture. Video blocks in an inter-coded (P or B) slice of a picture may use spatial prediction with respect to reference samples in neighboring blocks in the same picture or temporal prediction with respect to reference samples in other reference pictures. Pictures may be referred to as frames, and reference pictures may be referred to as reference frames.

Spatial or temporal prediction results in a predictive block for a block to be coded. Residual data represents pixel differences between the original block to be coded and the predictive block. An inter-coded block is encoded according to a motion vector that points to a block of reference samples forming the predictive block, and the residual data indicating the difference between the coded block and the predictive block. An intra-coded block is encoded according to an intra-coding mode and the residual data. For further compression, the residual data may be transformed from the pixel domain to a transform domain, resulting in residual transform coefficients, which then may be quantized. The quantized transform coefficients, initially arranged in a two-dimensional array, may be scanned in order to produce a one-dimensional vector of transform coefficients, and entropy encoding may be applied to achieve even more compression.

SUMMARY

Scalable video coding (SVC) refers to video coding in which a base layer (BL), sometimes referred to as a reference layer (RL), and one or more scalable enhancement layers (ELs) are used. In SVC, the base layer can carry video data with a base level of quality. The one or more enhancement layers can carry additional video data to support, for example, higher spatial, temporal, and/or signal-to-noise (SNR) levels. Enhancement layers may be defined relative to a previously encoded layer. For example, a bottom layer may serve as a BL, while a top layer may serve as an EL. Middle layers may serve as either ELs or RLs, or both. For example, a middle layer (e.g., a layer that is neither the lowest layer nor the highest layer) may be an EL for the layers below the middle layer, such as the base layer or any intervening enhancement layers, and at the same time serve as a RL for one or more enhancement layers above the middle layer. Similarly, in the Multiview or 3D extension of the HEVC standard, there may be multiple views, and information of one view may be utilized to code (e.g., encode or decode) the information of another view (e.g., motion estimation, motion vector prediction and/or other redundancies).

In SVC, the parameters used by the encoder or the decoder are grouped into parameter sets based on the coding level (e.g., video-level, sequence-level, picture-level, slice level, etc.) in which they may be utilized. For example, parameters that may be utilized by one or more coded video sequences in the bitstream may be included in a video parameter set (VPS), and parameters that are utilized by one or more pictures in a coded video sequence may be included in a sequence parameter set (SPS). Similarly, parameters that are utilized by one or more slices in a picture may be included in a picture parameter set (PPS), and other parameters that are specific to a single slice may be included in a slice header. Similarly, the indication of which parameter set(s) a particular layer is using at a given time may be provided at various coding levels. For example, if the slice header of a slice in the particular layer refers to a PPS, the PPS is activated for the slice or the picture containing the slice. Similarly, if the PPS refers to an SPS, the SPS is activated for the picture or the coded video sequence containing the picture, and if the SPS refers to a VPS, the VPS is activated for the coded video sequence or the video layer containing the coded video sequence.

Typically, a parameter set remains active (e.g., is currently being used for decoding a particular segment of the bitstream) for the entire coding level at which the parameter set is utilized. For example, an activated SPS may remain active for the entire sequence that initially activated the SPS, and an activated PPS may remain active for the entire picture that initially activated the PPS. However, in some existing coding schemes, a parameter set may be activated in the middle of the coding level at which another parameter set is currently active. In such a case, some of the parameters (e.g., picture resolution) that should remain constant for the duration of the coding process of the particular coding level (e.g., sequence, picture, slice, etc.) may be altered by the activation of the new parameter set and may result in undesired outcomes.

Thus, a coding scheme that manages the activation of parameter sets more efficiently and thereby improves coding accuracy and error resilience is desired.

The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein.

In one aspect, an apparatus configured to code (e.g., encode or decode) video information includes a memory unit and a processor in communication with the memory unit. The memory unit is configured to store video information associated with a reference layer (RL) and an enhancement layer (EL), the RL having an RL picture in a first access unit, and the EL having a first EL picture in the first access unit, wherein the first EL picture is associated with a first set of parameters. The processor is configured to determine whether the first EL picture is an intra random access point (IRAP) picture, determine whether the first access unit immediately follows a splice point where first video information is joined with second video information including the first EL picture, and perform, based on the determination of whether the first EL picture is an intra random access point (IRAP) picture and whether the first access unit immediately follows a splice point, one of (1) refraining from associating the first EL picture with a second set of parameters that is different from the first set of parameters, or (2) associating the first EL picture with a second set of parameters that is different from the first set of parameters.

In another aspect, a method of encoding video information comprises determining whether a first enhancement layer (EL) picture in a first access unit of an EL is an intra random access point (IRAP) picture, the first EL picture associated with a first set of parameters, determining whether the first access unit immediately follows a splice point where first video information is joined with second video information including the first EL picture, and performing, based on the determination of whether the first EL picture is an intra random access point (IRAP) picture and whether the first access unit immediately follows a splice point, one of (1) refraining from associating the first EL picture with a second set of parameters that is different from the first set of parameters, or (2) associating the first EL picture with a second set of parameters that is different from the first set of parameters.

In another aspect, a non-transitory computer readable medium comprises code that, when executed, causes an apparatus to perform a process. The process includes storing video information associated with a reference layer (RL) and an enhancement layer (EL), the RL having an RL picture in a first access unit, and the EL having a first EL picture in the first access unit, wherein the first EL picture is associated with a first set of parameters, determining whether the first EL picture is an intra random access point (IRAP) picture, determining whether the first access unit immediately follows a splice point where first video information is joined with second video information including the first EL picture, and performing, based on the determination of whether the first EL picture is an intra random access point (IRAP) picture and whether the first access unit immediately follows a splice point, one of (1) refraining from associating the first EL picture with a second set of parameters that is different from the first set of parameters, or (2) associating the first EL picture with a second set of parameters that is different from the first set of parameters.

In another aspect, a video coding device configured to code video information comprises means for storing video information associated with a reference layer (RL) and an enhancement layer (EL), the RL having an RL picture in a first access unit, and the EL having a first EL picture in the first access unit, wherein the first EL picture is associated with a first set of parameters, means for determining whether the first EL picture is an intra random access point (IRAP) picture, means for determining whether the first access unit immediately follows a splice point where first video information is joined with second video information including the first EL picture, and means for performing, based on the determination of whether the first EL picture is an intra random access point (IRAP) picture and whether the first access unit immediately follows a splice point, one of (1) refraining from associating the first EL picture with a second set of parameters that is different from the first set of parameters, or (2) associating the first EL picture with a second set of parameters that is different from the first set of parameters.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A is a block diagram illustrating an example video encoding and decoding system that may utilize techniques in accordance with aspects described in this disclosure.

FIG. 1B is a block diagram illustrating another example video encoding and decoding system that may perform techniques in accordance with aspects described in this disclosure.

FIG. 2A is a block diagram illustrating an example of a video encoder that may implement techniques in accordance with aspects described in this disclosure.

FIG. 2B is a block diagram illustrating an example of a video encoder that may implement techniques in accordance with aspects described in this disclosure.

FIG. 3A is a block diagram illustrating an example of a video decoder that may implement techniques in accordance with aspects described in this disclosure.

FIG. 3B is a block diagram illustrating an example of a video decoder that may implement techniques in accordance with aspects described in this disclosure.

FIG. 4 is a block diagram illustrating an example configuration of pictures in different layers, according to one embodiment of the present disclosure.

FIG. 5 illustrates a flow chart illustrating a method of coding video information, according to one embodiment of the present disclosure.

DETAILED DESCRIPTION

Certain embodiments described herein relate to inter-layer prediction for scalable video coding in the context of advanced video codecs, such as HEVC (High Efficiency Video Coding). More specifically, the present disclosure relates to systems and methods for improved performance of inter-layer prediction in scalable video coding (SVC) extension of HEVC.

In the description below, H.264/AVC techniques related to certain embodiments are described; the HEVC standard and related techniques are also discussed. While certain embodiments are described herein in the context of the HEVC and/or H.264 standards, one having ordinary skill in the art may appreciate that systems and methods disclosed herein may be applicable to any suitable video coding standard. For example, embodiments disclosed herein may be applicable to one or more of the following standards: ITU-T H.261, ISO/IEC MPEG-1 Visual, ITU-T H.262 or ISO/IEC MPEG-2 Visual, ITU-T H.263, ISO/IEC MPEG-4 Visual and ITU-T H.264 (also known as ISO/IEC MPEG-4 AVC), including its Scalable Video Coding (SVC) and Multiview Video Coding (MVC) extensions.

HEVC generally follows the framework of previous video coding standards in many respects. The unit of prediction in HEVC is different from that in certain previous video coding standards (e.g., macroblock). In fact, the concept of macroblock does not exist in HEVC as understood in certain previous video coding standards. Macroblock is replaced by a hierarchical structure based on a quadtree scheme, which may provide high flexibility, among other possible benefits. For example, within the HEVC scheme, three types of blocks, Coding Unit (CU), Prediction Unit (PU), and Transform Unit (TU), are defined. CU may refer to the basic unit of region splitting. CU may be considered analogous to the concept of macroblock, but HEVC does not restrict the maximum size of CUs and may allow recursive splitting into four equal size CUs to improve the content adaptivity. PU may be considered the basic unit of inter/intra prediction, and a single PU may contain multiple arbitrary shape partitions to effectively code irregular image patterns. TU may be considered the basic unit of transform. TU can be defined independently from the PU; however, the size of a TU may be limited to the size of the CU to which the TU belongs. This separation of the block structure into three different concepts may allow each unit to be optimized according to the respective role of the unit, which may result in improved coding efficiency.

For purposes of illustration only, certain embodiments disclosed herein are described with examples including only two layers (e.g., a lower layer such as the base layer, and a higher layer such as the enhancement layer). It should be understood that such examples may be applicable to configurations including multiple base and/or enhancement layers. In addition, for ease of explanation, the following disclosure includes the terms “frames” or “blocks” with reference to certain embodiments. However, these terms are not meant to be limiting. For example, the techniques described below can be used with any suitable video units, such as blocks (e.g., CU, PU, TU, macroblocks, etc.), slices, frames, etc.

Video Coding Standards

A digital image, such as a video image, a TV image, a still image or an image generated by a video recorder or a computer, may consist of pixels or samples arranged in horizontal and vertical lines. The number of pixels in a single image is typically in the tens of thousands. Each pixel typically contains luminance and chrominance information. Without compression, the sheer quantity of information to be conveyed from an image encoder to an image decoder would render real-time image transmission impossible. To reduce the amount of information to be transmitted, a number of different compression methods, such as JPEG, MPEG and H.263 standards, have been developed.

Video coding standards include ITU-T H.261, ISO/IEC MPEG-1 Visual, ITU-T H.262 or ISO/IEC MPEG-2 Visual, ITU-T H.263, ISO/IEC MPEG-4 Visual and ITU-T H.264 (also known as ISO/IEC MPEG-4 AVC), including its Scalable Video Coding (SVC) and Multiview Video Coding (MVC) extensions.

In addition, a new video coding standard, namely High Efficiency Video Coding (HEVC), is being developed by the Joint Collaboration Team on Video Coding (JCT-VC) of ITU-T Video Coding Experts Group (VCEG) and ISO/IEC Motion Picture Experts Group (MPEG). The full citation for the HEVC Draft 10 is document JCTVC-L1003, Bross et al., “High Efficiency Video Coding (HEVC) Text Specification Draft 10,” Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG16 WP3 and ISO/IEC JTC1/SC29/WG11, 12th Meeting: Geneva, Switzerland, Jan. 14, 2013 to Jan. 23, 2013. The multiview extension to HEVC, namely MV-HEVC, and the scalable extension to HEVC, named SHVC, are also being developed by the JCT-3V (ITU-T/ISO/IEC Joint Collaborative Team on 3D Video Coding Extension Development) and JCT-VC, respectively.

Various aspects of the novel systems, apparatuses, and methods are described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the novel systems, apparatuses, and methods disclosed herein, whether implemented independently of, or combined with, any other aspect of the present disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the present disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the present disclosure set forth herein. It should be understood that any aspect disclosed herein may be embodied by one or more elements of a claim.

Although particular aspects are described herein, many variations and permutations of these aspects fall within the scope of the disclosure. Although some benefits and advantages of the preferred aspects are mentioned, the scope of the disclosure is not intended to be limited to particular benefits, uses, or objectives. Rather, aspects of the disclosure are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transmission protocols, some of which are illustrated by way of example in the figures and in the following description of the preferred aspects. The detailed description and drawings are merely illustrative of the disclosure rather than limiting, the scope of the disclosure being defined by the appended claims and equivalents thereof.

The attached drawings illustrate examples. Elements indicated by reference numbers in the attached drawings correspond to elements indicated by like reference numbers in the following description. In this disclosure, elements having names that start with ordinal words (e.g., “first,” “second,” “third,” and so on) do not necessarily imply that the elements have a particular order. Rather, such ordinal words are merely used to refer to different elements of a same or similar type.

Video Coding System

FIG. 1A is a block diagram that illustrates an example video coding system 10 that may utilize techniques in accordance with aspects described in this disclosure. As used described herein, the term “video coder” refers generically to both video encoders and video decoders. In this disclosure, the terms “video coding” or “coding” may refer generically to video encoding and video decoding. In addition to video encoders and video decoders, the aspects described in the present application may be extended to other related devices such as transcoders (e.g., devices that can decode a bitstream and re-encode another bitstream) and middleboxes (e.g., devices that can modify, transform, and/or otherwise manipulate a bitstream).

As shown in FIG. 1A, video coding system 10 includes a source module 12 that generates encoded video data to be decoded at a later time by a destination module 14. In the example of FIG. 1A, the source module 12 and destination module 14 are on separate devices—specifically, the source module 12 is part of a source device, and the destination module 14 is part of a destination device. It is noted, however, that the source and destination modules 12, 14 may be on or part of the same device, as shown in the example of FIG. 1B.

With reference once again, to FIG. 1A, the source module 12 and the destination module 14 may comprise any of a wide range of devices, including desktop computers, notebook (e.g., laptop) computers, tablet computers, set-top boxes, telephone handsets such as so-called “smart” phones, so-called “smart” pads, televisions, cameras, display devices, digital media players, video gaming consoles, video streaming device, or the like. In some cases, the source module 12 and the destination module 14 may be equipped for wireless communication.

The destination module 14 may receive the encoded video data to be decoded via a link 16. The link 16 may comprise any type of medium or device capable of moving the encoded video data from the source module 12 to the destination module 14. In the example of FIG. 1A, the link 16 may comprise a communication medium to enable the source module 12 to transmit encoded video data directly to the destination module 14 in real-time. The encoded video data may be modulated according to a communication standard, such as a wireless communication protocol, and transmitted to the destination module 14. The communication medium may comprise any wireless or wired communication medium, such as a radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network, such as a local area network, a wide-area network, or a global network such as the Internet. The communication medium may include routers, switches, base stations, or any other equipment that may be useful to facilitate communication from the source module 12 to the destination module 14.

Alternatively, encoded data may be output from an output interface 22 to an optional storage device 31. Similarly, encoded data may be accessed from the storage device 31 by an input interface 28. The storage device 31 may include any of a variety of distributed or locally accessed data storage media such as a hard drive, flash memory, volatile or non-volatile memory, or any other suitable digital storage media for storing encoded video data. In a further example, the storage device 31 may correspond to a file server or another intermediate storage device that may hold the encoded video generated by the source module 12. The destination module 14 may access stored video data from the storage device 31 via streaming or download. The file server may be any type of server capable of storing encoded video data and transmitting that encoded video data to the destination module 14. Example file servers include a web server (e.g., for a website), an FTP server, network attached storage (NAS) devices, or a local disk drive. The destination module 14 may access the encoded video data through any standard data connection, including an Internet connection. This may include a wireless channel (e.g., a Wi-Fi connection), a wired connection (e.g., DSL, cable modem, etc.), or a combination of both that is suitable for accessing encoded video data stored on a file server. The transmission of encoded video data from the storage device 31 may be a streaming transmission, a download transmission, or a combination of both.

The techniques of this disclosure are not limited to wireless applications or settings. The techniques may be applied to video coding in support of any of a variety of multimedia applications, such as over-the-air television broadcasts, cable television transmissions, satellite television transmissions, streaming video transmissions, e.g., via the Internet (e.g., dynamic adaptive streaming over HTTP (DASH), etc.), encoding of digital video for storage on a data storage medium, decoding of digital video stored on a data storage medium, or other applications. In some examples, video coding system 10 may be configured to support one-way or two-way video transmission to support applications such as video streaming, video playback, video broadcasting, and/or video telephony.

In the example of FIG. 1A, the source module 12 includes a video source 18, video encoder 20 and an output interface 22. In some cases, the output interface 22 may include a modulator/demodulator (modem) and/or a transmitter. In the source module 12, the video source 18 may include a source such as a video capture device, e.g., a video camera, a video archive containing previously captured video, a video feed interface to receive video from a video content provider, and/or a computer graphics system for generating computer graphics data as the source video, or a combination of such sources. As one example, if the video source 18 is a video camera, the source module 12 and the destination module 14 may form so-called camera phones or video phones, as illustrated in the example of FIG. 1B. However, the techniques described in this disclosure may be applicable to video coding in general, and may be applied to wireless and/or wired applications.

The captured, pre-captured, or computer-generated video may be encoded by the video encoder 20. The encoded video data may be transmitted directly to the destination module 14 via the output interface 22 of the source module 12. The encoded video data may also (or alternatively) be stored onto the storage device 31 for later access by the destination module 14 or other devices, for decoding and/or playback. The video encoder 20 illustrated in FIGS. 1A and 1B may comprise the video encoder 20 illustrated FIG. 2A, the video encoder 23 illustrated in FIG. 2B, or any other video encoder described herein.

In the example of FIG. 1A, the destination module 14 includes an input interface 28, a video decoder 30, and a display device 32. In some cases, the input interface 28 may include a receiver and/or a modem. The input interface 28 of the destination module 14 may receive the encoded video data over the link 16. The encoded video data communicated over the link 16, or provided on the storage device 31, may include a variety of syntax elements generated by the video encoder 20 for use by a video decoder, such as the video decoder 30, in decoding the video data. Such syntax elements may be included with the encoded video data transmitted on a communication medium, stored on a storage medium, or stored a file server. The video decoder 30 illustrated in FIGS. 1A and 1B may comprise the video decoder 30 illustrated FIG. 3A, the video decoder 33 illustrated in FIG. 3B, or any other video decoder described herein.

The display device 32 may be integrated with, or external to, the destination module 14. In some examples, the destination module 14 may include an integrated display device and also be configured to interface with an external display device. In other examples, the destination module 14 may be a display device. In general, the display device 32 displays the decoded video data to a user, and may comprise any of a variety of display devices such as a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, or another type of display device.

In related aspects, FIG. 1B shows an example video encoding and decoding system 10′ wherein the source and destination modules 12, 14 are on or part of a device or user device 11. The device 11 may be a telephone handset, such as a “smart” phone or the like. The device 11 may include an optional controller/processor module 13 in operative communication with the source and destination modules 12, 14. The system 10′ of FIG. 1B may further include a video processing unit 21 between the video encoder 20 and the output interface 22. In some implementations, the video processing unit 21 is a separate unit, as illustrated in FIG. 1B; however, in other implementations, the video processing unit 21 can be implemented as a portion of the video encoder 20 and/or the processor/controller module 13. The system 10′ may also include an optional tracker 29, which can track an object of interest in a video sequence. The object or interest to be tracked may be segmented by a technique described in connection with one or more aspects of the present disclosure. In related aspects, the tracking may be performed by the display device 32, alone or in conjunction with the tracker 29. The system 10′ of FIG. 1B, and components thereof, are otherwise similar to the system 10 of FIG. 1A, and components thereof.

Video encoder 20 and video decoder 30 may operate according to a video compression standard, such as the High Efficiency Video Coding (HEVC) standard presently under development, and may conform to a HEVC Test Model (HM). Alternatively, video encoder 20 and video decoder 30 may operate according to other proprietary or industry standards, such as the ITU-T H.264 standard, alternatively referred to as MPEG-4, Part 10, Advanced Video Coding (AVC), or extensions of such standards. The techniques of this disclosure, however, are not limited to any particular coding standard. Other examples of video compression standards include MPEG-2 and ITU-T H.263.

Although not shown in the examples of FIGS. 1A and 1B, video encoder 20 and video decoder 30 may each be integrated with an audio encoder and decoder, and may include appropriate MUX-DEMUX units, or other hardware and software, to handle encoding of both audio and video in a common data stream or separate data streams. If applicable, in some examples, MUX-DEMUX units may conform to the ITU H.223 multiplexer protocol, or other protocols such as the user datagram protocol (UDP).

The video encoder 20 and the video decoder 30 each may be implemented as any of a variety of suitable encoder circuitry, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware or any combinations thereof. When the techniques are implemented partially in software, a device may store instructions for the software in a suitable, non-transitory computer-readable medium and execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Each of the video encoder 20 and the video decoder 30 may be included in one or more encoders or decoders, either of which may be integrated as part of a combined encoder/decoder (CODEC) in a respective device.

Video Coding Process

As mentioned briefly above, video encoder 20 encodes video data. The video data may comprise one or more pictures. Each of the pictures is a still image forming part of a video. In some instances, a picture may be referred to as a video “frame.” When video encoder 20 encodes the video data, video encoder 20 may generate a bitstream. The bitstream may include a sequence of bits that form a coded representation of the video data. The bitstream may include coded pictures and associated data. A coded picture is a coded representation of a picture.

To generate the bitstream, video encoder 20 may perform encoding operations on each picture in the video data. When video encoder 20 performs encoding operations on the pictures, video encoder 20 may generate a series of coded pictures and associated data. The associated data may include video parameter sets (VPS), sequence parameter sets, picture parameter sets, adaptation parameter sets, and other syntax structures. A sequence parameter set (SPS) may contain parameters applicable to zero or more sequences of pictures. A picture parameter set (PPS) may contain parameters applicable to zero or more pictures. An adaptation parameter set (APS) may contain parameters applicable to zero or more pictures. Parameters in an APS may be parameters that are more likely to change than parameters in a PPS.

To generate a coded picture, video encoder 20 may partition a picture into equally-sized video blocks. A video block may be a two-dimensional array of samples. Each of the video blocks is associated with a treeblock. In some instances, a treeblock may be referred to as a largest coding unit (LCU). The treeblocks of HEVC may be broadly analogous to the macroblocks of previous standards, such as H.264/AVC. However, a treeblock is not necessarily limited to a particular size and may include one or more coding units (CUs). Video encoder 20 may use quadtree partitioning to partition the video blocks of treeblocks into video blocks associated with CUs, hence the name “treeblocks.”

In some examples, video encoder 20 may partition a picture into a plurality of slices. Each of the slices may include an integer number of CUs. In some instances, a slice comprises an integer number of treeblocks. In other instances, a boundary of a slice may be within a treeblock.

As part of performing an encoding operation on a picture, video encoder 20 may perform encoding operations on each slice of the picture. When video encoder 20 performs an encoding operation on a slice, video encoder 20 may generate encoded data associated with the slice. The encoded data associated with the slice may be referred to as a “coded slice.”

To generate a coded slice, video encoder 20 may perform encoding operations on each treeblock in a slice. When video encoder 20 performs an encoding operation on a treeblock, video encoder 20 may generate a coded treeblock. The coded treeblock may comprise data representing an encoded version of the treeblock.

When video encoder 20 generates a coded slice, video encoder 20 may perform encoding operations on (e.g., encode) the treeblocks in the slice according to a raster scan order. For example, video encoder 20 may encode the treeblocks of the slice in an order that proceeds from left to right across a topmost row of treeblocks in the slice, then from left to right across a next lower row of treeblocks, and so on until video encoder 20 has encoded each of the treeblocks in the slice.

As a result of encoding the treeblocks according to the raster scan order, the treeblocks above and to the left of a given treeblock may have been encoded, but treeblocks below and to the right of the given treeblock have not yet been encoded. Consequently, video encoder 20 may be able to access information generated by encoding treeblocks above and to the left of the given treeblock when encoding the given treeblock. However, video encoder 20 may be unable to access information generated by encoding treeblocks below and to the right of the given treeblock when encoding the given treeblock.

To generate a coded treeblock, video encoder 20 may recursively perform quadtree partitioning on the video block of the treeblock to divide the video block into progressively smaller video blocks. Each of the smaller video blocks may be associated with a different CU. For example, video encoder 20 may partition the video block of a treeblock into four equally-sized sub-blocks, partition one or more of the sub-blocks into four equally-sized sub-sub-blocks, and so on. A partitioned CU may be a CU whose video block is partitioned into video blocks associated with other CUs. A non-partitioned CU may be a CU whose video block is not partitioned into video blocks associated with other CUs.

One or more syntax elements in the bitstream may indicate a maximum number of times video encoder 20 may partition the video block of a treeblock. A video block of a CU may be square in shape. The size of the video block of a CU (e.g., the size of the CU) may range from 8×8 pixels up to the size of a video block of a treeblock (e.g., the size of the treeblock) with a maximum of 64×64 pixels or greater.

Video encoder 20 may perform encoding operations on (e.g., encode) each CU of a treeblock according to a z-scan order. In other words, video encoder 20 may encode a top-left CU, a top-right CU, a bottom-left CU, and then a bottom-right CU, in that order. When video encoder 20 performs an encoding operation on a partitioned CU, video encoder 20 may encode CUs associated with sub-blocks of the video block of the partitioned CU according to the z-scan order. In other words, video encoder 20 may encode a CU associated with a top-left sub-block, a CU associated with a top-right sub-block, a CU associated with a bottom-left sub-block, and then a CU associated with a bottom-right sub-block, in that order.

As a result of encoding the CUs of a treeblock according to a z-scan order, the CUs above, above-and-to-the-left, above-and-to-the-right, left, and below-and-to-the left of a given CU may have been encoded. CUs below and to the right of the given CU have not yet been encoded. Consequently, video encoder 20 may be able to access information generated by encoding some CUs that neighbor the given CU when encoding the given CU. However, video encoder 20 may be unable to access information generated by encoding other CUs that neighbor the given CU when encoding the given CU.

When video encoder 20 encodes a non-partitioned CU, video encoder 20 may generate one or more prediction units (PUs) for the CU. Each of the PUs of the CU may be associated with a different video block within the video block of the CU. Video encoder 20 may generate a predicted video block for each PU of the CU. The predicted video block of a PU may be a block of samples. Video encoder 20 may use intra prediction or inter prediction to generate the predicted video block for a PU.

When video encoder 20 uses intra prediction to generate the predicted video block of a PU, video encoder 20 may generate the predicted video block of the PU based on decoded samples of the picture associated with the PU. If video encoder 20 uses intra prediction to generate predicted video blocks of the PUs of a CU, the CU is an intra-predicted CU. When video encoder 20 uses inter prediction to generate the predicted video block of the PU, video encoder 20 may generate the predicted video block of the PU based on decoded samples of one or more pictures other than the picture associated with the PU. If video encoder 20 uses inter prediction to generate predicted video blocks of the PUs of a CU, the CU is an inter-predicted CU.

Furthermore, when video encoder 20 uses inter prediction to generate a predicted video block for a PU, video encoder 20 may generate motion information for the PU. The motion information for a PU may indicate one or more reference blocks of the PU. Each reference block of the PU may be a video block within a reference picture. The reference picture may be a picture other than the picture associated with the PU. In some instances, a reference block of a PU may also be referred to as the “reference sample” of the PU. Video encoder 20 may generate the predicted video block for the PU based on the reference blocks of the PU.

After video encoder 20 generates predicted video blocks for one or more PUs of a CU, video encoder 20 may generate residual data for the CU based on the predicted video blocks for the PUs of the CU. The residual data for the CU may indicate differences between samples in the predicted video blocks for the PUs of the CU and the original video block of the CU.

Furthermore, as part of performing an encoding operation on a non-partitioned CU, video encoder 20 may perform recursive quadtree partitioning on the residual data of the CU to partition the residual data of the CU into one or more blocks of residual data (e.g., residual video blocks) associated with transform units (TUs) of the CU. Each TU of a CU may be associated with a different residual video block.

Video encoder 20 may apply one or more transforms to residual video blocks associated with the TUs to generate transform coefficient blocks (e.g., blocks of transform coefficients) associated with the TUs. Conceptually, a transform coefficient block may be a two-dimensional (2D) matrix of transform coefficients.

After generating a transform coefficient block, video encoder 20 may perform a quantization process on the transform coefficient block. Quantization generally refers to a process in which transform coefficients are quantized to possibly reduce the amount of data used to represent the transform coefficients, providing further compression. The quantization process may reduce the bit depth associated with some or all of the transform coefficients. For example, an n-bit transform coefficient may be rounded down to an m-bit transform coefficient during quantization, where n is greater than m.

Video encoder 20 may associate each CU with a quantization parameter (QP) value. The QP value associated with a CU may determine how video encoder 20 quantizes transform coefficient blocks associated with the CU. Video encoder 20 may adjust the degree of quantization applied to the transform coefficient blocks associated with a CU by adjusting the QP value associated with the CU.

After video encoder 20 quantizes a transform coefficient block, video encoder 20 may generate sets of syntax elements that represent the transform coefficients in the quantized transform coefficient block. Video encoder 20 may apply entropy encoding operations, such as Context Adaptive Binary Arithmetic Coding (CABAC) operations, to some of these syntax elements. Other entropy coding techniques such as content adaptive variable length coding (CAVLC), probability interval partitioning entropy (PIPE) coding, or other binary arithmetic coding could also be used.

The bitstream generated by video encoder 20 may include a series of Network Abstraction Layer (NAL) units. Each of the NAL units may be a syntax structure containing an indication of a type of data in the NAL unit and bytes containing the data. For example, a NAL unit may contain data representing a video parameter set, a sequence parameter set, a picture parameter set, a coded slice, supplemental enhancement information (SEI), an access unit delimiter, filler data, or another type of data. The data in a NAL unit may include various syntax structures.

Video decoder 30 may receive the bitstream generated by video encoder 20. The bitstream may include a coded representation of the video data encoded by video encoder 20. When video decoder 30 receives the bitstream, video decoder 30 may perform a parsing operation on the bitstream. When video decoder 30 performs the parsing operation, video decoder 30 may extract syntax elements from the bitstream. Video decoder 30 may reconstruct the pictures of the video data based on the syntax elements extracted from the bitstream. The process to reconstruct the video data based on the syntax elements may be generally reciprocal to the process performed by video encoder 20 to generate the syntax elements.

After video decoder 30 extracts the syntax elements associated with a CU, video decoder 30 may generate predicted video blocks for the PUs of the CU based on the syntax elements. In addition, video decoder 30 may inverse quantize transform coefficient blocks associated with TUs of the CU. Video decoder 30 may perform inverse transforms on the transform coefficient blocks to reconstruct residual video blocks associated with the TUs of the CU. After generating the predicted video blocks and reconstructing the residual video blocks, video decoder 30 may reconstruct the video block of the CU based on the predicted video blocks and the residual video blocks. In this way, video decoder 30 may reconstruct the video blocks of CUs based on the syntax elements in the bitstream.

Video Encoder

FIG. 2A is a block diagram illustrating an example of a video encoder that may implement techniques in accordance with aspects described in this disclosure. Video encoder 20 may be configured to process a single layer of a video frame, such as for HEVC. Further, video encoder 20 may be configured to perform any or all of the techniques of this disclosure. As one example, prediction processing unit 100 may be configured to perform any or all of the techniques described in this disclosure. In another embodiment, the video encoder 20 includes an optional inter-layer prediction unit 128 that is configured to perform any or all of the techniques described in this disclosure. In other embodiments, inter-layer prediction can be performed by prediction processing unit 100 (e.g., inter prediction unit 121 and/or intra prediction unit 126), in which case the inter-layer prediction unit 128 may be omitted. However, aspects of this disclosure are not so limited. In some examples, the techniques described in this disclosure may be shared among the various components of video encoder 20. In some examples, additionally or alternatively, a processor (not shown) may be configured to perform any or all of the techniques described in this disclosure.

For purposes of explanation, this disclosure describes video encoder 20 in the context of HEVC coding. However, the techniques of this disclosure may be applicable to other coding standards or methods. The example depicted in FIG. 2A is for a single layer codec. However, as will be described further with respect to FIG. 2B, some or all of the video encoder 20 may be duplicated for processing of a multi-layer codec.

Video encoder 20 may perform intra- and inter-coding of video blocks within video slices. Intra coding relies on spatial prediction to reduce or remove spatial redundancy in video within a given video frame or picture. Inter-coding relies on temporal prediction to reduce or remove temporal redundancy in video within adjacent frames or pictures of a video sequence. Intra-mode (I mode) may refer to any of several spatial based coding modes. Inter-modes, such as uni-directional prediction (P mode) or bi-directional prediction (B mode), may refer to any of several temporal-based coding modes.

In the example of FIG. 2A, video encoder 20 includes a plurality of functional components. The functional components of video encoder 20 include a prediction processing unit 100, a residual generation unit 102, a transform processing unit 104, a quantization unit 106, an inverse quantization unit 108, an inverse transform unit 110, a reconstruction unit 112, a filter unit 113, a decoded picture buffer 114, and an entropy encoding unit 116. Prediction processing unit 100 includes an inter prediction unit 121, a motion estimation unit 122, a motion compensation unit 124, an intra prediction unit 126, and an inter-layer prediction unit 128. In other examples, video encoder 20 may include more, fewer, or different functional components. Furthermore, motion estimation unit 122 and motion compensation unit 124 may be highly integrated, but are represented in the example of FIG. 2A separately for purposes of explanation.

Video encoder 20 may receive video data. Video encoder 20 may receive the video data from various sources. For example, video encoder 20 may receive the video data from video source 18 (e.g., shown in FIG. 1A or 1B) or another source. The video data may represent a series of pictures. To encode the video data, video encoder 20 may perform an encoding operation on each of the pictures. As part of performing the encoding operation on a picture, video encoder 20 may perform encoding operations on each slice of the picture. As part of performing an encoding operation on a slice, video encoder 20 may perform encoding operations on treeblocks in the slice.

As part of performing an encoding operation on a treeblock, prediction processing unit 100 may perform quadtree partitioning on the video block of the treeblock to divide the video block into progressively smaller video blocks. Each of the smaller video blocks may be associated with a different CU. For example, prediction processing unit 100 may partition a video block of a treeblock into four equally-sized sub-blocks, partition one or more of the sub-blocks into four equally-sized sub-sub-blocks, and so on.

The sizes of the video blocks associated with CUs may range from 8×8 samples up to the size of the treeblock with a maximum of 64×64 samples or greater. In this disclosure, “N×N” and “N by N” may be used interchangeably to refer to the sample dimensions of a video block in terms of vertical and horizontal dimensions, e.g., 16×16 samples or 16 by 16 samples. In general, a 16×16 video block has sixteen samples in a vertical direction (y=16) and sixteen samples in a horizontal direction (x=16). Likewise, an N×N block generally has N samples in a vertical direction and N samples in a horizontal direction, where N represents a nonnegative integer value.

Furthermore, as part of performing the encoding operation on a treeblock, prediction processing unit 100 may generate a hierarchical quadtree data structure for the treeblock. For example, a treeblock may correspond to a root node of the quadtree data structure. If prediction processing unit 100 partitions the video block of the treeblock into four sub-blocks, the root node has four child nodes in the quadtree data structure. Each of the child nodes corresponds to a CU associated with one of the sub-blocks. If prediction processing unit 100 partitions one of the sub-blocks into four sub-sub-blocks, the node corresponding to the CU associated with the sub-block may have four child nodes, each of which corresponds to a CU associated with one of the sub-sub-blocks.

Each node of the quadtree data structure may contain syntax data (e.g., syntax elements) for the corresponding treeblock or CU. For example, a node in the quadtree may include a split flag that indicates whether the video block of the CU corresponding to the node is partitioned (e.g., split) into four sub-blocks. Syntax elements for a CU may be defined recursively, and may depend on whether the video block of the CU is split into sub-blocks. A CU whose video block is not partitioned may correspond to a leaf node in the quadtree data structure. A coded treeblock may include data based on the quadtree data structure for a corresponding treeblock.

Video encoder 20 may perform encoding operations on each non-partitioned CU of a treeblock. When video encoder 20 performs an encoding operation on a non-partitioned CU, video encoder 20 generates data representing an encoded representation of the non-partitioned CU.

As part of performing an encoding operation on a CU, prediction processing unit 100 may partition the video block of the CU among one or more PUs of the CU. Video encoder 20 and video decoder 30 may support various PU sizes. Assuming that the size of a particular CU is 2N×2N, video encoder 20 and video decoder 30 may support PU sizes of 2N×2N or N×N, and inter-prediction in symmetric PU sizes of 2N×2N, 2N×N, N×2N, N×N, 2N×nU, nL×2N, nR×2N, or similar. Video encoder 20 and video decoder 30 may also support asymmetric partitioning for PU sizes of 2N×nU, 2N×nD, nL×2N, and nR×2N. In some examples, prediction processing unit 100 may perform geometric partitioning to partition the video block of a CU among PUs of the CU along a boundary that does not meet the sides of the video block of the CU at right angles.

Inter prediction unit 121 may perform inter prediction on each PU of the CU. Inter prediction may provide temporal compression. To perform inter prediction on a PU, motion estimation unit 122 may generate motion information for the PU. Motion compensation unit 124 may generate a predicted video block for the PU based the motion information and decoded samples of pictures other than the picture associated with the CU (e.g., reference pictures). In this disclosure, a predicted video block generated by motion compensation unit 124 may be referred to as an inter-predicted video block.

Slices may be I slices, P slices, or B slices. Motion estimation unit 122 and motion compensation unit 124 may perform different operations for a PU of a CU depending on whether the PU is in an I slice, a P slice, or a B slice. In an I slice, all PUs are intra predicted. Hence, if the PU is in an I slice, motion estimation unit 122 and motion compensation unit 124 do not perform inter prediction on the PU.

If the PU is in a P slice, the picture containing the PU is associated with a list of reference pictures referred to as “list 0.” Each of the reference pictures in list 0 contains samples that may be used for inter prediction of other pictures. When motion estimation unit 122 performs the motion estimation operation with regard to a PU in a P slice, motion estimation unit 122 may search the reference pictures in list 0 for a reference block for the PU. The reference block of the PU may be a set of samples, e.g., a block of samples, that most closely corresponds to the samples in the video block of the PU. Motion estimation unit 122 may use a variety of metrics to determine how closely a set of samples in a reference picture corresponds to the samples in the video block of a PU. For example, motion estimation unit 122 may determine how closely a set of samples in a reference picture corresponds to the samples in the video block of a PU by sum of absolute difference (SAD), sum of square difference (SSD), or other difference metrics.

After identifying a reference block of a PU in a P slice, motion estimation unit 122 may generate a reference index that indicates the reference picture in list 0 containing the reference block and a motion vector that indicates a spatial displacement between the PU and the reference block. In various examples, motion estimation unit 122 may generate motion vectors to varying degrees of precision. For example, motion estimation unit 122 may generate motion vectors at one-quarter sample precision, one-eighth sample precision, or other fractional sample precision. In the case of fractional sample precision, reference block values may be interpolated from integer-position sample values in the reference picture. Motion estimation unit 122 may output the reference index and the motion vector as the motion information of the PU. Motion compensation unit 124 may generate a predicted video block of the PU based on the reference block identified by the motion information of the PU.

If the PU is in a B slice, the picture containing the PU may be associated with two lists of reference pictures, referred to as “list 0” and “list 1.” In some examples, a picture containing a B slice may be associated with a list combination that is a combination of list 0 and list 1.

Furthermore, if the PU is in a B slice, motion estimation unit 122 may perform uni-directional prediction or bi-directional prediction for the PU. When motion estimation unit 122 performs uni-directional prediction for the PU, motion estimation unit 122 may search the reference pictures of list 0 or list 1 for a reference block for the PU. Motion estimation unit 122 may then generate a reference index that indicates the reference picture in list 0 or list 1 that contains the reference block and a motion vector that indicates a spatial displacement between the PU and the reference block. Motion estimation unit 122 may output the reference index, a prediction direction indicator, and the motion vector as the motion information of the PU. The prediction direction indicator may indicate whether the reference index indicates a reference picture in list 0 or list 1. Motion compensation unit 124 may generate the predicted video block of the PU based on the reference block indicated by the motion information of the PU.

When motion estimation unit 122 performs bi-directional prediction for a PU, motion estimation unit 122 may search the reference pictures in list 0 for a reference block for the PU and may also search the reference pictures in list 1 for another reference block for the PU. Motion estimation unit 122 may then generate reference indexes that indicate the reference pictures in list 0 and list 1 containing the reference blocks and motion vectors that indicate spatial displacements between the reference blocks and the PU. Motion estimation unit 122 may output the reference indexes and the motion vectors of the PU as the motion information of the PU. Motion compensation unit 124 may generate the predicted video block of the PU based on the reference blocks indicated by the motion information of the PU.

In some instances, motion estimation unit 122 does not output a full set of motion information for a PU to entropy encoding unit 116. Rather, motion estimation unit 122 may signal the motion information of a PU with reference to the motion information of another PU. For example, motion estimation unit 122 may determine that the motion information of the PU is sufficiently similar to the motion information of a neighboring PU. In this example, motion estimation unit 122 may indicate, in a syntax structure associated with the PU, a value that indicates to video decoder 30 that the PU has the same motion information as the neighboring PU. In another example, motion estimation unit 122 may identify, in a syntax structure associated with the PU, a neighboring PU and a motion vector difference (MVD). The motion vector difference indicates a difference between the motion vector of the PU and the motion vector of the indicated neighboring PU. Video decoder 30 may use the motion vector of the indicated neighboring PU and the motion vector difference to determine the motion vector of the PU. By referring to the motion information of a first PU when signaling the motion information of a second PU, video encoder 20 may be able to signal the motion information of the second PU using fewer bits.

As further discussed below with reference to FIG. 4, the prediction processing unit 100 may be configured to code (e.g., encode or decode) the PU (or any other reference layer and/or enhancement layer blocks or video units) by performing the methods illustrated in FIG. 4. For example, inter prediction unit 121 (e.g., via motion estimation unit 122 and/or motion compensation unit 124), intra prediction unit 126, or inter-layer prediction unit 128 may be configured to perform the methods illustrated in FIG. 4, either together or separately.

As part of performing an encoding operation on a CU, intra prediction unit 126 may perform intra prediction on PUs of the CU. Intra prediction may provide spatial compression. When intra prediction unit 126 performs intra prediction on a PU, intra prediction unit 126 may generate prediction data for the PU based on decoded samples of other PUs in the same picture. The prediction data for the PU may include a predicted video block and various syntax elements. Intra prediction unit 126 may perform intra prediction on PUs in I slices, P slices, and B slices.

To perform intra prediction on a PU, intra prediction unit 126 may use multiple intra prediction modes to generate multiple sets of prediction data for the PU. When intra prediction unit 126 uses an intra prediction mode to generate a set of prediction data for the PU, intra prediction unit 126 may extend samples from video blocks of neighboring PUs across the video block of the PU in a direction and/or gradient associated with the intra prediction mode. The neighboring PUs may be above, above and to the right, above and to the left, or to the left of the PU, assuming a left-to-right, top-to-bottom encoding order for PUs, CUs, and treeblocks. Intra prediction unit 126 may use various numbers of intra prediction modes, e.g., 33 directional intra prediction modes, depending on the size of the PU.

Prediction processing unit 100 may select the prediction data for a PU from among the prediction data generated by motion compensation unit 124 for the PU or the prediction data generated by intra prediction unit 126 for the PU. In some examples, prediction processing unit 100 selects the prediction data for the PU based on rate/distortion metrics of the sets of prediction data.

If prediction processing unit 100 selects prediction data generated by intra prediction unit 126, prediction processing unit 100 may signal the intra prediction mode that was used to generate the prediction data for the PUs, e.g., the selected intra prediction mode. Prediction processing unit 100 may signal the selected intra prediction mode in various ways. For example, it may be probable that the selected intra prediction mode is the same as the intra prediction mode of a neighboring PU. In other words, the intra prediction mode of the neighboring PU may be the most probable mode for the current PU. Thus, prediction processing unit 100 may generate a syntax element to indicate that the selected intra prediction mode is the same as the intra prediction mode of the neighboring PU.

As discussed above, the video encoder 20 may include inter-layer prediction unit 128. Inter-layer prediction unit 128 is configured to predict a current block (e.g., a current block in the EL) using one or more different layers that are available in SVC (e.g., a base or reference layer). Such prediction may be referred to as inter-layer prediction. Inter-layer prediction unit 128 utilizes prediction methods to reduce inter-layer redundancy, thereby improving coding efficiency and reducing computational resource requirements. Some examples of inter-layer prediction include inter-layer intra prediction, inter-layer motion prediction, and inter-layer residual prediction. Inter-layer intra prediction uses the reconstruction of co-located blocks in the base layer to predict the current block in the enhancement layer. Inter-layer motion prediction uses motion information of the base layer to predict motion in the enhancement layer. Inter-layer residual prediction uses the residue of the base layer to predict the residue of the enhancement layer. Each of the inter-layer prediction schemes is discussed below in greater detail.

After prediction processing unit 100 selects the prediction data for PUs of a CU, residual generation unit 102 may generate residual data for the CU by subtracting (e.g., indicated by the minus sign) the predicted video blocks of the PUs of the CU from the video block of the CU. The residual data of a CU may include 2D residual video blocks that correspond to different sample components of the samples in the video block of the CU. For example, the residual data may include a residual video block that corresponds to differences between luminance components of samples in the predicted video blocks of the PUs of the CU and luminance components of samples in the original video block of the CU. In addition, the residual data of the CU may include residual video blocks that correspond to the differences between chrominance components of samples in the predicted video blocks of the PUs of the CU and the chrominance components of the samples in the original video block of the CU.

Prediction processing unit 100 may perform quadtree partitioning to partition the residual video blocks of a CU into sub-blocks. Each undivided residual video block may be associated with a different TU of the CU. The sizes and positions of the residual video blocks associated with TUs of a CU may or may not be based on the sizes and positions of video blocks associated with the PUs of the CU. A quadtree structure known as a “residual quad tree” (RQT) may include nodes associated with each of the residual video blocks. The TUs of a CU may correspond to leaf nodes of the RQT.

Transform processing unit 104 may generate one or more transform coefficient blocks for each TU of a CU by applying one or more transforms to a residual video block associated with the TU. Each of the transform coefficient blocks may be a 2D matrix of transform coefficients. Transform processing unit 104 may apply various transforms to the residual video block associated with a TU. For example, transform processing unit 104 may apply a discrete cosine transform (DCT), a directional transform, or a conceptually similar transform to the residual video block associated with a TU.

After transform processing unit 104 generates a transform coefficient block associated with a TU, quantization unit 106 may quantize the transform coefficients in the transform coefficient block. Quantization unit 106 may quantize a transform coefficient block associated with a TU of a CU based on a QP value associated with the CU.

Video encoder 20 may associate a QP value with a CU in various ways. For example, video encoder 20 may perform a rate-distortion analysis on a treeblock associated with the CU. In the rate-distortion analysis, video encoder 20 may generate multiple coded representations of the treeblock by performing an encoding operation multiple times on the treeblock. Video encoder 20 may associate different QP values with the CU when video encoder 20 generates different encoded representations of the treeblock. Video encoder 20 may signal that a given QP value is associated with the CU when the given QP value is associated with the CU in a coded representation of the treeblock that has a lowest bitrate and distortion metric.

Inverse quantization unit 108 and inverse transform unit 110 may apply inverse quantization and inverse transforms to the transform coefficient block, respectively, to reconstruct a residual video block from the transform coefficient block. Reconstruction unit 112 may add the reconstructed residual video block to corresponding samples from one or more predicted video blocks generated by prediction processing unit 100 to produce a reconstructed video block associated with a TU. By reconstructing video blocks for each TU of a CU in this way, video encoder 20 may reconstruct the video block of the CU.

After reconstruction unit 112 reconstructs the video block of a CU, filter unit 113 may perform a deblocking operation to reduce blocking artifacts in the video block associated with the CU. After performing the one or more deblocking operations, filter unit 113 may store the reconstructed video block of the CU in decoded picture buffer 114. Motion estimation unit 122 and motion compensation unit 124 may use a reference picture that contains the reconstructed video block to perform inter prediction on PUs of subsequent pictures. In addition, intra prediction unit 126 may use reconstructed video blocks in decoded picture buffer 114 to perform intra prediction on other PUs in the same picture as the CU.

Entropy encoding unit 116 may receive data from other functional components of video encoder 20. For example, entropy encoding unit 116 may receive transform coefficient blocks from quantization unit 106 and may receive syntax elements from prediction processing unit 100. When entropy encoding unit 116 receives the data, entropy encoding unit 116 may perform one or more entropy encoding operations to generate entropy encoded data. For example, video encoder 20 may perform a context adaptive variable length coding (CAVLC) operation, a CABAC operation, a variable-to-variable (V2V) length coding operation, a syntax-based context-adaptive binary arithmetic coding (SBAC) operation, a Probability Interval Partitioning Entropy (PIPE) coding operation, or another type of entropy encoding operation on the data. Entropy encoding unit 116 may output a bitstream that includes the entropy encoded data.

As part of performing an entropy encoding operation on data, entropy encoding unit 116 may select a context model. If entropy encoding unit 116 is performing a CABAC operation, the context model may indicate estimates of probabilities of particular bins having particular values. In the context of CABAC, the term “bin” is used to refer to a bit of a binarized version of a syntax element.

Multi-Layer Video Encoder

FIG. 2B is a block diagram illustrating an example of a multi-layer video encoder 23 that may implement techniques in accordance with aspects described in this disclosure. The video encoder 23 may be configured to process multi-layer video frames, such as for SHVC and multiview coding. Further, the video encoder 23 may be configured to perform any or all of the techniques of this disclosure.

The video encoder 23 includes a video encoder 20A and video encoder 20B, each of which may be configured as the video encoder 20 and may perform the functions described above with respect to the video encoder 20. Further, as indicated by the reuse of reference numbers, the video encoders 20A and 20B may include at least some of the systems and subsystems as the video encoder 20. Although the video encoder 23 is illustrated as including two video encoders 20A and 20B, the video encoder 23 is not limited as such and may include any number of video encoder 20 layers. In some embodiments, the video encoder 23 may include a video encoder 20 for each picture or frame in an access unit. For example, an access unit that includes five pictures may be processed or encoded by a video encoder that includes five encoder layers. In some embodiments, the video encoder 23 may include more encoder layers than frames in an access unit. In some such cases, some of the video encoder layers may be inactive when processing some access units.

In addition to the video encoders 20A and 20B, the video encoder 23 may include an resampling unit 90. The resampling unit 90 may, in some cases, upsample a base layer of a received video frame to, for example, create an enhancement layer. The resampling unit 90 may upsample particular information associated with the received base layer of a frame, but not other information. For example, the resampling unit 90 may upsample the spatial size or number of pixels of the base layer, but the number of slices or the picture order count may remain constant. In some cases, the resampling unit 90 may not process the received video and/or may be optional. For example, in some cases, the prediction processing unit 100 may perform upsampling. In some embodiments, the resampling unit 90 is configured to upsample a layer and reorganize, redefine, modify, or adjust one or more slices to comply with a set of slice boundary rules and/or raster scan rules. Although primarily described as upsampling a base layer, or a lower layer in an access unit, in some cases, the resampling unit 90 may downsample a layer. For example, if during streaming of a video bandwidth is reduced, a frame may be downsampled instead of upsampled.

The resampling unit 90 may be configured to receive a picture or frame (or picture information associated with the picture) from the decoded picture buffer 114 of the lower layer encoder (e.g., the video encoder 20A) and to upsample the picture (or the received picture information). This upsampled picture may then be provided to the prediction processing unit 100 of a higher layer encoder (e.g., the video encoder 20B) configured to encode a picture in the same access unit as the lower layer encoder. In some cases, the higher layer encoder is one layer removed from the lower layer encoder. In other cases, there may be one or more higher layer encoders between the layer 0 video encoder and the layer 1 encoder of FIG. 2B.

In some cases, the resampling unit 90 may be omitted or bypassed. In such cases, the picture from the decoded picture buffer 114 of the video encoder 20A may be provided directly, or at least without being provided to the resampling unit 90, to the prediction processing unit 100 of the video encoder 20B. For example, if video data provided to the video encoder 20B and the reference picture from the decoded picture buffer 114 of the video encoder 20A are of the same size or resolution, the reference picture may be provided to the video encoder 20B without any resampling.

In some embodiments, the video encoder 23 downsamples video data to be provided to the lower layer encoder using the downsampling unit 94 before provided the video data to the video encoder 20A. Alternatively, the downsampling unit 94 may be a resampling unit 90 capable of upsampling or downsampling the video data. In yet other embodiments, the downsampling unit 94 may be omitted.

As illustrated in FIG. 2B, the video encoder 23 may further include a multiplexor 98, or mux. The mux 98 can output a combined bitstream from the video encoder 23. The combined bitstream may be created by taking a bitstream from each of the video encoders 20A and 20B and alternating which bitstream is output at a given time. While in some cases the bits from the two (or more in the case of more than two video encoder layers) bitstreams may be alternated one bit at a time, in many cases the bitstreams are combined differently. For example, the output bitstream may be created by alternating the selected bitstream one block at a time. In another example, the output bitstream may be created by outputting a non-1:1 ratio of blocks from each of the video encoders 20A and 20B. For instance, two blocks may be output from the video encoder 20B for each block output from the video encoder 20A. In some embodiments, the output stream from the mux 98 may be preprogrammed. In other embodiments, the mux 98 may combine the bitstreams from the video encoders 20A, 20B based on a control signal received from a system external to the video encoder 23, such as from a processor on a source device including the source module 12. The control signal may be generated based on the resolution or bitrate of a video from the video source 18, based on a bandwidth of the link 16, based on a subscription associated with a user (e.g., a paid subscription versus a free subscription), or based on any other factor for determining a resolution output desired from the video encoder 23.

Video Decoder

FIG. 3A is a block diagram illustrating an example of a video decoder that may implement techniques in accordance with aspects described in this disclosure. The video decoder 30 may be configured to process a single layer of a video frame, such as for HEVC. Further, video decoder 30 may be configured to perform any or all of the techniques of this disclosure. As one example, motion compensation unit 162 and/or intra prediction unit 164 may be configured to perform any or all of the techniques described in this disclosure. In one embodiment, video decoder 30 may optionally include inter-layer prediction unit 166 that is configured to perform any or all of the techniques described in this disclosure. In other embodiments, inter-layer prediction can be performed by prediction processing unit 152 (e.g., motion compensation unit 162 and/or intra prediction unit 164), in which case the inter-layer prediction unit 166 may be omitted. However, aspects of this disclosure are not so limited. In some examples, the techniques described in this disclosure may be shared among the various components of video decoder 30. In some examples, additionally or alternatively, a processor (not shown) may be configured to perform any or all of the techniques described in this disclosure.

For purposes of explanation, this disclosure describes video decoder 30 in the context of HEVC coding. However, the techniques of this disclosure may be applicable to other coding standards or methods. The example depicted in FIG. 3A is for a single layer codec. However, as will be described further with respect to FIG. 3B, some or all of the video decoder 30 may be duplicated for processing of a multi-layer codec.

In the example of FIG. 3A, video decoder 30 includes a plurality of functional components. The functional components of video decoder 30 include an entropy decoding unit 150, a prediction processing unit 152, an inverse quantization unit 154, an inverse transform unit 156, a reconstruction unit 158, a filter unit 159, and a decoded picture buffer 160. Prediction processing unit 152 includes a motion compensation unit 162, an intra prediction unit 164, and an inter-layer prediction unit 166. In some examples, video decoder 30 may perform a decoding pass generally reciprocal to the encoding pass described with respect to video encoder 20 of FIG. 2A. In other examples, video decoder 30 may include more, fewer, or different functional components.

Video decoder 30 may receive a bitstream that comprises encoded video data. The bitstream may include a plurality of syntax elements. When video decoder 30 receives the bitstream, entropy decoding unit 150 may perform a parsing operation on the bitstream. As a result of performing the parsing operation on the bitstream, entropy decoding unit 150 may extract syntax elements from the bitstream. As part of performing the parsing operation, entropy decoding unit 150 may entropy decode entropy encoded syntax elements in the bitstream. Prediction processing unit 152, inverse quantization unit 154, inverse transform unit 156, reconstruction unit 158, and filter unit 159 may perform a reconstruction operation that generates decoded video data based on the syntax elements extracted from the bitstream.

As discussed above, the bitstream may comprise a series of NAL units. The NAL units of the bitstream may include video parameter set NAL units, sequence parameter set NAL units, picture parameter set NAL units, SEI NAL units, and so on. As part of performing the parsing operation on the bitstream, entropy decoding unit 150 may perform parsing operations that extract and entropy decode sequence parameter sets from sequence parameter set NAL units, picture parameter sets from picture parameter set NAL units, SEI data from SEI NAL units, and so on.

In addition, the NAL units of the bitstream may include coded slice NAL units. As part of performing the parsing operation on the bitstream, entropy decoding unit 150 may perform parsing operations that extract and entropy decode coded slices from the coded slice NAL units. Each of the coded slices may include a slice header and slice data. The slice header may contain syntax elements pertaining to a slice. The syntax elements in the slice header may include a syntax element that identifies a picture parameter set associated with a picture that contains the slice. Entropy decoding unit 150 may perform entropy decoding operations, such as CABAC decoding operations, on syntax elements in the coded slice header to recover the slice header.

As part of extracting the slice data from coded slice NAL units, entropy decoding unit 150 may perform parsing operations that extract syntax elements from coded CUs in the slice data. The extracted syntax elements may include syntax elements associated with transform coefficient blocks. Entropy decoding unit 150 may then perform CABAC decoding operations on some of the syntax elements.

After entropy decoding unit 150 performs a parsing operation on a non-partitioned CU, video decoder 30 may perform a reconstruction operation on the non-partitioned CU. To perform the reconstruction operation on a non-partitioned CU, video decoder 30 may perform a reconstruction operation on each TU of the CU. By performing the reconstruction operation for each TU of the CU, video decoder 30 may reconstruct a residual video block associated with the CU.

As part of performing a reconstruction operation on a TU, inverse quantization unit 154 may inverse quantize, e.g., de-quantize, a transform coefficient block associated with the TU. Inverse quantization unit 154 may inverse quantize the transform coefficient block in a manner similar to the inverse quantization processes proposed for HEVC or defined by the H.264 decoding standard. Inverse quantization unit 154 may use a quantization parameter QP calculated by video encoder 20 for a CU of the transform coefficient block to determine a degree of quantization and, likewise, a degree of inverse quantization for inverse quantization unit 154 to apply.

After inverse quantization unit 154 inverse quantizes a transform coefficient block, inverse transform unit 156 may generate a residual video block for the TU associated with the transform coefficient block. Inverse transform unit 156 may apply an inverse transform to the transform coefficient block in order to generate the residual video block for the TU. For example, inverse transform unit 156 may apply an inverse DCT, an inverse integer transform, an inverse Karhunen-Loeve transform (KLT), an inverse rotational transform, an inverse directional transform, or another inverse transform to the transform coefficient block. In some examples, inverse transform unit 156 may determine an inverse transform to apply to the transform coefficient block based on signaling from video encoder 20. In such examples, inverse transform unit 156 may determine the inverse transform based on a signaled transform at the root node of a quadtree for a treeblock associated with the transform coefficient block. In other examples, inverse transform unit 156 may infer the inverse transform from one or more coding characteristics, such as block size, coding mode, or the like. In some examples, inverse transform unit 156 may apply a cascaded inverse transform.

In some examples, motion compensation unit 162 may refine the predicted video block of a PU by performing interpolation based on interpolation filters. Identifiers for interpolation filters to be used for motion compensation with sub-sample precision may be included in the syntax elements. Motion compensation unit 162 may use the same interpolation filters used by video encoder 20 during generation of the predicted video block of the PU to calculate interpolated values for sub-integer samples of a reference block. Motion compensation unit 162 may determine the interpolation filters used by video encoder 20 according to received syntax information and use the interpolation filters to produce the predicted video block.

As further discussed below with reference to FIG. 4, the prediction processing unit 152 may code (e.g., encode or decode) the PU (or any other reference layer and/or enhancement layer blocks or video units) by performing the methods illustrated in FIG. 4. For example, motion compensation unit 162, intra prediction unit 164, or inter-layer prediction unit 166 may be configured to perform the methods illustrated in FIG. 4, either together or separately.

If a PU is encoded using intra prediction, intra prediction unit 164 may perform intra prediction to generate a predicted video block for the PU. For example, intra prediction unit 164 may determine an intra prediction mode for the PU based on syntax elements in the bitstream. The bitstream may include syntax elements that intra prediction unit 164 may use to determine the intra prediction mode of the PU.

In some instances, the syntax elements may indicate that intra prediction unit 164 is to use the intra prediction mode of another PU to determine the intra prediction mode of the current PU. For example, it may be probable that the intra prediction mode of the current PU is the same as the intra prediction mode of a neighboring PU. In other words, the intra prediction mode of the neighboring PU may be the most probable mode for the current PU. Hence, in this example, the bitstream may include a small syntax element that indicates that the intra prediction mode of the PU is the same as the intra prediction mode of the neighboring PU. Intra prediction unit 164 may then use the intra prediction mode to generate prediction data (e.g., predicted samples) for the PU based on the video blocks of spatially neighboring PUs.

As discussed above, video decoder 30 may also include inter-layer prediction unit 166. Inter-layer prediction unit 166 is configured to predict a current block (e.g., a current block in the EL) using one or more different layers that are available in SVC (e.g., a base or reference layer). Such prediction may be referred to as inter-layer prediction. Inter-layer prediction unit 166 utilizes prediction methods to reduce inter-layer redundancy, thereby improving coding efficiency and reducing computational resource requirements. Some examples of inter-layer prediction include inter-layer intra prediction, inter-layer motion prediction, and inter-layer residual prediction. Inter-layer intra prediction uses the reconstruction of co-located blocks in the base layer to predict the current block in the enhancement layer. Inter-layer motion prediction uses motion information of the base layer to predict motion in the enhancement layer. Inter-layer residual prediction uses the residue of the base layer to predict the residue of the enhancement layer. Each of the inter-layer prediction schemes is discussed below in greater detail.

Reconstruction unit 158 may use the residual video blocks associated with TUs of a CU and the predicted video blocks of the PUs of the CU, e.g., either intra-prediction data or inter-prediction data, as applicable, to reconstruct the video block of the CU. Thus, video decoder 30 may generate a predicted video block and a residual video block based on syntax elements in the bitstream and may generate a video block based on the predicted video block and the residual video block.

After reconstruction unit 158 reconstructs the video block of the CU, filter unit 159 may perform a deblocking operation to reduce blocking artifacts associated with the CU. After filter unit 159 performs a deblocking operation to reduce blocking artifacts associated with the CU, video decoder 30 may store the video block of the CU in decoded picture buffer 160. Decoded picture buffer 160 may provide reference pictures for subsequent motion compensation, intra prediction, and presentation on a display device, such as display device 32 of FIG. 1A or 1B. For instance, video decoder 30 may perform, based on the video blocks in decoded picture buffer 160, intra prediction or inter prediction operations on PUs of other CUs.

Multi-Layer Decoder

FIG. 3B is a block diagram illustrating an example of a multi-layer video decoder 33 that may implement techniques in accordance with aspects described in this disclosure. The video decoder 33 may be configured to process multi-layer video frames, such as for SHVC and multiview coding. Further, the video decoder 33 may be configured to perform any or all of the techniques of this disclosure.

The video decoder 33 includes a video decoder 30A and video decoder 30B, each of which may be configured as the video decoder 30 and may perform the functions described above with respect to the video decoder 30. Further, as indicated by the reuse of reference numbers, the video decoders 30A and 30B may include at least some of the systems and subsystems as the video decoder 30. Although the video decoder 33 is illustrated as including two video decoders 30A and 30B, the video decoder 33 is not limited as such and may include any number of video decoder 30 layers. In some embodiments, the video decoder 33 may include a video decoder 30 for each picture or frame in an access unit. For example, an access unit that includes five pictures may be processed or decoded by a video decoder that includes five decoder layers. In some embodiments, the video decoder 33 may include more decoder layers than frames in an access unit. In some such cases, some of the video decoder layers may be inactive when processing some access units.

In addition to the video decoders 30A and 30B, the video decoder 33 may include an upsampling unit 92. In some embodiments, the upsampling unit 92 may upsample a base layer of a received video frame to create an enhanced layer to be added to the reference picture list for the frame or access unit. This enhanced layer can be stored in the decoded picture buffer 160. In some embodiments, the upsampling unit 92 can include some or all of the embodiments described with respect to the resampling unit 90 of FIG. 2A. In some embodiments, the upsampling unit 92 is configured to upsample a layer and reorganize, redefine, modify, or adjust one or more slices to comply with a set of slice boundary rules and/or raster scan rules. In some cases, the upsampling unit 92 may be a resampling unit configured to upsample and/or downsample a layer of a received video frame

The upsampling unit 92 may be configured to receive a picture or frame (or picture information associated with the picture) from the decoded picture buffer 160 of the lower layer decoder (e.g., the video decoder 30A) and to upsample the picture (or the received picture information). This upsampled picture may then be provided to the prediction processing unit 152 of a higher layer decoder (e.g., the video decoder 30B) configured to decode a picture in the same access unit as the lower layer decoder. In some cases, the higher layer decoder is one layer removed from the lower layer decoder. In other cases, there may be one or more higher layer decoders between the layer 0 decoder and the layer 1 decoder of FIG. 3B.

In some cases, the upsampling unit 92 may be omitted or bypassed. In such cases, the picture from the decoded picture buffer 160 of the video decoder 30A may be provided directly, or at least without being provided to the upsampling unit 92, to the prediction processing unit 152 of the video decoder 30B. For example, if video data provided to the video decoder 30B and the reference picture from the decoded picture buffer 160 of the video decoder 30A are of the same size or resolution, the reference picture may be provided to the video decoder 30B without upsampling. Further, in some embodiments, the upsampling unit 92 may be a resampling unit 90 configured to upsample or downsample a reference picture received from the decoded picture buffer 160 of the video decoder 30A.

As illustrated in FIG. 3B, the video decoder 33 may further include a demultiplexor 99, or demux. The demux 99 can split an encoded video bitstream into multiple bitstreams with each bitstream output by the demux 99 being provided to a different video decoder 30A and 30B. The multiple bitstreams may be created by receiving a bitstream and each of the video decoders 30A and 30B receives a portion of the bitstream at a given time. While in some cases the bits from the bitstream received at the demux 99 may be alternated one bit at a time between each of the video decoders (e.g., video decoders 30A and 30B in the example of FIG. 3B), in many cases the bitstream is divided differently. For example, the bitstream may be divided by alternating which video decoder receives the bitstream one block at a time. In another example, the bitstream may be divided by a non-1:1 ratio of blocks to each of the video decoders 30A and 30B. For instance, two blocks may be provided to the video decoder 30B for each block provided to the video decoder 30A. In some embodiments, the division of the bitstream by the demux 99 may be preprogrammed. In other embodiments, the demux 99 may divide the bitstream based on a control signal received from a system external to the video decoder 33, such as from a processor on a destination device including the destination module 14. The control signal may be generated based on the resolution or bitrate of a video from the input interface 28, based on a bandwidth of the link 16, based on a subscription associated with a user (e.g., a paid subscription versus a free subscription), or based on any other factor for determining a resolution obtainable by the video decoder 33.

Intra Random Access Point (IRAP) Pictures

Some video coding schemes may provide various random access points throughout the bitstream such that the bitstream may be decoded starting from any of those random access points without needing to decode any pictures that precede those random access points in the bitstream. In such video coding schemes, all pictures that follow a random access point in output order (e.g., including those pictures that are in the same access unit as the picture providing the random access point) can be correctly decoded without using any pictures that precede the random access point. For example, even if a portion of the bitstream is lost during transmission or during decoding, a decoder can resume decoding the bitstream starting from the next random access point. Support for random access may facilitate, for example, dynamic streaming services, seek operations, channel switching, etc.

In some coding schemes, such random access points may be provided by pictures that are referred to as intra random access point (IRAP) pictures. For example, a random access point (e.g., provided by an enhancement layer IRAP picture) in an enhancement layer (“layerA”) contained in an access unit (“auA”) may provide layer-specific random access such that for each reference layer (“layerB”) of layerA (e.g., a reference layer being a layer that is used to predict layerA) having a random access point contained in an access unit (“auB”) that is in layerB and precedes auA in decoding order (or a random access point contained in auA), the pictures in layerA that follow auB in output order (including those pictures located in auB), are correctly decodable without needing to decode any pictures in layerA that precede auB.

IRAP pictures may be coded using intra prediction (e.g., coded without referring to other pictures) or inter-layer prediction, and may include, for example, instantaneous decoder refresh (IDR) pictures, clean random access (CRA) pictures, and broken link access (BLA) pictures. When there is an IDR picture in the bitstream, all the pictures that precede the IDR picture in decoding order are not used for prediction by pictures that follow the IDR picture. When there is a CRA picture in the bitstream, the pictures that follow the CRA picture may or may not use pictures that precede the CRA picture in decoding order for prediction. Those pictures that follow the CRA picture in decoding order but use pictures that precede the CRA picture in decoding order may be referred to as random access skipped leading (RASL) pictures. Another type of picture that can follow an IRAP picture in decoding order and precede it in output order is a random access decodable leading (RADL) picture, which may not contain references to any pictures that precede the IRAP picture in decoding order. RASL pictures may be discarded by the decoder if the pictures that precede the CRA picture are not available. A BLA picture indicates to the decoder that pictures that precede the BLA picture may not be available to the decoder (e.g., because two bitstreams are spliced together and the BLA picture is the first picture of the second bitstream in decoding order). An access unit (e.g., a group of pictures consisting of all the coded pictures associated with the same output time across multiple layers) containing a base layer picture (e.g., having a layer ID value of “0”) that is an IRAP picture may be referred to as an IRAP access unit.

Network Abstraction Layer (NAL) Units and Parameter Sets

As discussed above, the parameters used by an encoder or a decoder may be grouped into parameter sets based on the coding level in which they may be utilized. For example, parameters that are utilized by one or more coded video sequences in the bitstream may be included in a video parameter set (VPS), and parameters that are utilized by one or more pictures in a coded video sequence may be included in a sequence parameter set (SPS). Similarly, parameters that are utilized by one or more slices in a picture may be included in a picture parameter set (PPS), and other parameters that are specific to a single slice may be included in a slice header. Similarly, the indication of which parameter set(s) a particular layer is using (e.g., active) at a given time may be provided at various coding levels. For example, if the slice header of a slice in the particular layer refers to a PPS, the PPS is activated for the slice or the picture containing the slice. Similarly, if the PPS refers to an SPS, the SPS is activated for the picture or the coded video sequence containing the picture, and if the SPS refers to a VPS, the VPS is activated for the coded video sequence or the video layer containing the coded video sequence.

Such parameter sets may be provided in a bitstream in the form of parameter set NAL units (e.g., SPS NAL unit, PPS NAL unit, etc.). A NAL unit may comprise a raw byte sequence payload (RBSP) and a NAL unit header. The RBSP may specify a parameter set ID (e.g., SPS ID), and the NAL unit header may specify the layer ID, which may indicate which layers may use the SPS.

Activation of Sequence Parameter Set (SPS) Raw Byte Sequence Payload (RBSP)

An SPS RBSP includes parameters that can be referred to by one or more picture parameter set (PPS) RBSPs or one or more SEI NAL units containing an active parameter sets SEI message. Each SPS RBSP may initially be considered to be not active for any layer at the start of the decoding process. For each layer, at most one SPS RBSP is considered to be active at any given moment during the decoding process, and the activation of any particular SPS RBSP for a particular layer results in the deactivation of the previously-active SPS RBSP for that particular layer, if any.

One SPS RBSP may be the active SPS RBSP for more than one layer. For example, if a base layer and an enhancement layer both contain a picture that refers to a PPS that in turn refers to an SPS having an SPS ID of 3, the SPS having an SPS ID of 3 is the active SPS RBSP for both the reference layer and the enhancement layer.

When an SPS RBSP (e.g., having a particular SPS ID) is not already active for a particular non-base layer (e.g., having a non-zero layer ID value or a layer ID greater than 0) having a layer ID (e.g., nuh_layer_id) of X, and the SPS RBSP is referred to by activation of a picture parameter set (PPS) RBSP (e.g., in which the PPS ID is equal to the particular SPS ID of the SPS RBSP), the SPS RBSP is activated for the particular non-base layer. This SPS may be referred to as the active SPS RBSP for the particular non-base layer until it is deactivated by the activation of another SPS RBSP for the particular non-base layer.

Layer Initialization Picture (LIP)

In some coding schemes, a layer initialization picture (“LIP picture”) may be defined as a picture that is an IRAP picture that has a NoRaslOutputFlag flag (e.g., a flag that indicates that RASL pictures are not to be output if the value is set to “1” and indicates that RASL pictures are to be output if the value is set to “0”) set to a value of “1” or a picture that is contained an initial IRAP access unit, which is an IRAP access unit in which the base layer picture (e.g., a picture having a layer ID value of “0” or smallest layer ID defined in the bitstream) has the NoRaslOutputFlag set to a value of “1”.

In some embodiments, an SPS can be activated at each LIP picture. For example, each IRAP picture that has a NoRaslOutputFlag flag set to a value of “1” or each picture that is contained in an initial IRAP access unit, a new SPS, which may be different (e.g., specifying different picture resolutions, etc.) from the SPS that was previously activated. However, in a case where the LIP picture is not an IRAP picture (e.g., any picture contained in an initial IRAP access unit) and the base layer picture in the initial IRAP access unit is an IDR picture with a flag NoClrasOutputFlag flag (e.g., a flag that indicates that cross-layer random access skip pictures are not to be output if the value is set to “1” and indicates that cross-layer random access skip pictures are to be output if the value is set to “0”) set to a value of “0”, the LIP picture should not be allowed to activate a new SPS. If a new SPS is activated at such the LIP picture in such a case, particularly when the contents of the SPS RBSP of the new SPS is different from that of the SPS that was previously active prior to the initial IRAP access unit, there could be problems in differing picture resolutions and error resilience. For example, the new SPS may update the resolution and use temporal prediction to refer to pictures of different sizes.

In some embodiments, NoClRasOutputFlag and NoRaslOutputFlag may be variables derived based on the information included in the bitstream. For example, NoRaslOutputFlag may be derived for every IRAP picture (e.g., in BL and/or EL), and NoClRasOutputFlag may be derived only for the lowest layer pictures (e.g., BL pictures). The value of each of NoClRasOutputFlag and NoRaslOutputFlag may indicate that some pictures in the bitstream may not be correctly decodable due to the unavailability of certain reference pictures. Such unavailability of reference pictures may occur at random access points. Cross-layer random access skip (CL-RAS) pictures are, in some ways, the multi-layer equivalent of RASL pictures. If a decoder starts decoding a bitstream at a random access point (e.g., an access unit having a BL IRAP picture), and the EL picture in the access unit is not an IRAP picture, then that EL picture is a CL-RAS picture. All pictures in the EL may be CL-RAS pictures (e.g., decodable, but not correctly decodable) until an IRAP picture occurs in the EL. When such an EL IRAP picture is provided in the bitstream, the EL may be said to have been initialized.

Duration of Active SPS RBSP

In order to prevent activation of a new SPS by a LIP picture that is a non-IRAP picture other than at a splice point, which may cause the problems described above, the activated SPS RBSP may be forced to remain active for a certain period of time. In some embodiments, an activated SPS RBSP for a particular layer is to remain active for the entire coded layer-wise video sequence (CLVS) of that particular layer. A CLVS may refer to a sequence of coded pictures, which are in the same layer (e.g., having the same layer ID value), that consists, in decoding order, of an IRAP picture with NoRaslOutputFlag equal to a value of “1” or a picture with FirstPicInLayerDecodedFlag equal to a value of “0” (e.g., indicating that the picture is the first picture in the layer), followed by all coded pictures, if any, up to but excluding the next IRAP picture with NoRaslOutputFlag equal to a value of “1” or the next picture with FirstPicInLayerDecodedFlag equal to a value of “0”.

In some embodiments, an activated SPS RBSP for a particular layer is to remain active for a sequence of pictures in decoding order in the particular layer as follows: (1) If the particular nuh_layer_id value is equal to 0, the activated SPS shall remain active for the entire CVS; and (2) otherwise (e.g., the layer ID of the particular layer is not equal to 0), the activated SPS is to remain active starting from an LIP picture that is an IRAP picture in the particular layer, or an LIP picture that is not an IRAP picture and that is contained in an IRAP access unit containing a base layer picture that is an IRAP picture and has a NoClrasOutputFlag value of “1”, until the next LIP picture that is an IRAP picture in the particular layer, or an initial IRAP access unit containing a base layer picture that is an IRAP picture and has a NoClrasOutputFlag value of “1”.

Bitstream Including a Splice Point

With reference to FIG. 4, an example bitstream having a splice point will be described. FIG. 4 shows a multi-layer bitstream 400 created by splicing bitstreams 410 and 420. The bitstream 410 includes an enhancement layer (EL) 410A and a base layer (BL) 410B, and the bitstream 420 includes an EL 420A and a BL 420B. The EL 410A includes an EL picture 412A, and the BL 410B includes a BL picture 412B. The EL 420A includes EL pictures 422A, 424A, and 426A, and the BL 420B includes BL pictures 422B, 424B, and 426B. The multi-layer bitstream 400 further includes access units (AUs) 430-460. The AU 430 includes the EL picture 412A and the BL picture 412B, the AU 440 includes the EL picture 422A and the BL picture 422B, the AU 450 includes the EL picture 424A and the BL picture 424B, and the AU 460 includes the EL picture 426A and the BL picture 426B. In the example of FIG. 4, the BL picture 422B is an IRAP picture, and the corresponding EL picture 422A in the AU 440 is a trailing picture (e.g., a non-IRAP picture), and consequently, the AU 440 is a non-aligned IRAP AU. Also, it should be noted that the AU 440 is an access unit that immediately follows a splice point 470.

Although the example of FIG. 4 illustrates a case where two different bitstreams are joined together, in some embodiments, a splice point may be present when a portion of the bitstream is removed. For example, a bitstream may have portions A, B, and C, portion B being between portions A and C. If portion B is removed from the bitstream, the remaining portions A and C may be joined together, and the point at which they are joined together may be referred to as a splice point. More generally, a splice point as discussed in the present application may be deemed to be present when one or more signaled or derived parameters or flags have predetermined values. For example, without receiving a specific indication that a splice point exists at a particular location, a decoder may determine the value of a flag (e.g., NoClrasOutputFlag), and perform one or more techniques described in this application based on the value of the flag.

Restricting Activation of New Parameter Set

FIG. 5 is a flowchart illustrating a method 500 for coding video information, according to an embodiment of the present disclosure. The steps illustrated in FIG. 5 may be performed by an encoder (e.g., the video encoder as shown in FIG. 2A or FIG. 2B), a decoder (e.g., the video decoder as shown in FIG. 3A or FIG. 3B), or any other component. For convenience, method 500 is described as performed by a coder, which may be the encoder, the decoder, or another component.

The method 500 begins at block 501. At block 505, the coder determines whether an enhancement layer (EL) picture is an IRAP picture. For example, if the EL picture is any of an IDR picture, a CRA picture, or a BLA picture, the coder may determine the EL picture to be an IRAP picture. In some embodiments, the coder determines that the EL picture is an IRAP picture by checking the NAL unit type associated with the EL picture. If the coder determines that the EL picture is an IRAP picture, the method 500 proceeds to block 520. If the coder determines that the EL picture is not an IRAP picture, the process 500 proceeds to block 510.

At block 510, the coder determines whether the EL picture is at a splice point. A splice point may indicate the point at which two bitstreams are joined. For example, the last picture of a first bitstream may be immediately followed, in coding order, by the first picture of a second bitstream. In some embodiments, the coder may determine whether the EL picture is at a splice point by determining whether the EL picture is the first picture that follows the splice point in coding order. If the coder determines that the EL picture is at a splice point, the method 500 proceeds to block 520. If the coder determines that the EL picture is not at a splice point, the method 500 proceeds to block 515. As discussed above with reference to FIG. 4, the determination in 510 may comprise determining whether one or more signaled or derived parameters or flags have predetermined values. For example, without receiving a specific indication that a splice point exists at a particular location, an encoder or a decoder may determine the value of a flag (e.g., NoClrasOutputFlag), and proceed to either block 515 or block 520 based on the determination.

At block 515, the coder disallows activation of a new parameter set. For example, the coder may prevent the EL picture from activating a new SPS. The coder may disallow activation of a new parameter set by causing the previously activated parameter set to remain active until the next IRAP picture in the EL is processed. Alternatively, the coder may disallow activation of a new parameter set by causing the previously activated parameter set to remain active until the next splice point. In yet another example, the coder may disallow activation of a new parameter set by causing the previously activated parameter set to remain active until the end of the coded video sequence containing the EL picture.

At block 520, the coder allows activation of a new parameter set. For example, the coder may cause the enhancement layer to be associated with a new parameter set that has different parameters than the parameter set that was previously activated for the EL. The method 500 ends at 525.

As discussed above, one or more components of video encoder 20 of FIG. 2A, video encoder 23 of FIG. 2B, video decoder 30 of FIG. 3A, or video decoder 33 of FIG. 3B (e.g., inter-layer prediction unit 128 and/or inter-layer prediction unit 166) may be used to implement any of the techniques discussed in the present disclosure, such as determining whether the EL picture is an IRAP picture, determining whether the EL picture is at a splice point, and disallowing or allowing activation of a new parameter set.

In the method 500, one or more of the blocks shown in FIG. 5 may be removed (e.g., not performed) and/or the order in which the method is performed may be switched. For example, although block 510 is shown in FIG. 5, it may be removed to simplify the coding process. Thus, the embodiments of the present disclosure are not limited to or by the example shown in FIG. 5, and other variations may be implemented without departing from the spirit of this disclosure.

Constraints on Never-Activated Parameter Sets

In some coding schemes, there may be bitstream conformance constraints (e.g., constraints that may be determined to be applicable and then adhered to by, for example, a coder) specified for active parameter sets (e.g., active PPS or active SPS), shown in italics: “pps_scaling_list_ref layer_id specifies the value of the nuh_layer_id of the layer for which the active PPS is associated with the same scaling list data as the current PPS. The value of pps_scaling_list_ref_layer_id shall be in the range of 0 to 62, inclusive. When avc_base_layer_flag is equal to 1, it is a requirement of bitstream conformance that pps_scaling_list_ref_layer_id shall be greater than 0. It is a requirement of bitstream conformance that, when a PPS with nuh_layer_id equal to nuhLayerIdA is active for a layer with nuh_layer_id equal to nuhLayerIdB and pps_infer_scaling_list_flag in the PPS is equal to 1, pps_infer_scaling_list_flag shall be equal to 0 for the PPS that is active for the layer with nuh_layer_id equal to pps_scaling_list_ref layer_id. It is a requirement of bitstream conformance that, when a PPS with nuh_layer_id equal to nuhLayerIdA is active for a layer with nuh_layer_id equal to nuhLayerIdB, the layer with nuh_layer_id equal to pps_scaling_list_ref_layer_id shall be a direct or indirect reference layer of the layer with nuh_layer_id equal to nuhLayerIdB.”

In some coding schemes, a parameter set that is never activated by any layer may nonetheless be required to satisfy the following constraints, shown in italics: “All constraints that are expressed on the relationship between the values of the syntax elements and the values of variables derived from those syntax elements in VPSs, SPSs, and PPSs and other syntax elements are expressions of constraints that apply only to the active VPS, the active SPS, and the active PPS. If any VPS RBSP, SPS RBSP, and PPS RBSP is present that is never activated in the bitstream, its syntax elements shall have values that would conform to the specified constraints if it was activated by reference in an otherwise conforming bitstream.”

However, for parameter sets such as VPS, SPS, PPS, etc. that are never activated, it may be difficult to check whether the first italicized constraints above are satisfied for parameter sets that are in a bitstream but never activated, even considering the second italicized constraint. This is because even if a given parameter set satisfies the constraints if activated for one layer, the same parameter set may fail to satisfy the constraints if activated for another layer. Multiple parameter sets can be signaled for a single layer through the bitstream (e.g., prior to activation, regardless of whether they are activated or not), so whether a particular bitstream is conformant cannot be determined unless those parameter sets are activated for one or more layers.

Changes to Constraints on Never-Activated Parameter Sets

In some embodiments, the conformance check is excluded from the bitstream conformance check the syntax element of the never-activated parameter set which bitstream conformance constraint depends on other syntax elements from other parameter sets. The constraint discussed above can be modified as follows: “If any VPS RBSP, SPS RBSP, and PPS RBSP is present that is never activated in the bitstream, syntax elements of that particular parameter set RBSP shall have values that would conform to those specified constraints that are not dependent on the value of any syntax element of another parameter set RBSP.”

In some embodiments, some particular syntax elements of the never-activated parameter set can be skipped from the bitstream conformance check according to some rule. For example, the conformance check checks the conformance constraint for the never-activated parameter set only for the layer for which this parameter set is signaled. The constraint discussed above can be modified as follows: “If any VPS RBSP, SPS RBSP, and PPS RBSP is present that is never activated in the bitstream, its syntax elements shall have values that would conform to the specified constraints if it was activated by reference with the layer Id signaled in the parameter set in an otherwise conforming bitstream.”

SPS Video Usability Information (VUI)

SPS VUI includes information such as sample aspect ratio, over scan, source video format (PAL/NTSC etc., sample value range, source color format), field/frame information, bitstream restrictions (including cross-layer bitstream restrictions). Such information may include cross-layer bitstream restrictions, which may not be layer-specific but instead apply to all layers. Thus, in some existing coding schemes, such information may be repeated in each SPS.

In some embodiments, all SPS VUI information may be included in VPS VUI, and if for a particular layer any VUI parameter for an SPS must have a different value than that in the VPS VUI, the entire SPS VUI may be directly signaled in the SPS. Otherwise, the SPS does not contain VUI parameters and the VUI is inferred from the VPS.

Example changes of syntax and semantics that may be implemented to facilitate the handling of the information described above, the following changes may be made, where additions are shown in italics:

TABLE 1 example syntax of vps_vui( ) Descriptor vps_vui( ){  ...  sps_vui_in_vps_flag u(1)  if( sps_vui_in_vps_flag )   vui_parameters( ) }

The semantics for sps_vui_in_vps_flag may read as follows: “sps_vui_in_vps_flag equal to 1 specifies that the vui_parameters( ) syntax structure is present in the VPS and applies to all SPSs that refer to the VPS and have sps_vui_from_vps_flag equal to 1. sps_vui_in_vps_flag equal to 0 specifies that the vui_parameters( ) syntax structure is not present in the VPS. When vps_vui_present_flag is equal to 0, the value of sps_vui_in_vps_flag is inferred to be equal to 0.”

TABLE 2 Example Syntax for seq_parameter_set_rbsp( ) Descriptor seq_parameter_set_rbsp( ) {  ...  if( nuh_layer_id > 0 )   sps_vui_from_vps_flag u(1)  if( !sps_vui_from_vps_flag )   vui_parameters_present_flag u(1)  if( vui_parameters_present_flag )   vui_parameters( )  sps_extension_flag u(1)  if( sps_extension_flag ) {   sps_extension( )   sps_extension2_flag u(1)   if( sps_extension2_flag )    while( more_rbsp_data( ) )     sps_extension_data_flag u(1)  }  rbsp_trailing_bits( ) }

The semantics for sps_vui_from_vps_flag may read as follows: “sps_vui_from_vps_flag equal to 1 specifies that the vui_parameters( ) syntax structure applicable to the SPS is inferred to be identical to that in the VPS the SPS refers to. sps_vui_from_vps_flag equal to 0 specifies that the vui_parameters( ) syntax structure applicable to the SPS is not inferred from the VPS the SPS refers to. When not present, the value of sps_vui_from_vps_flag is inferred to be equal to 0. When sps_vui_in_vps_flag is equal to 0, the value of sps_vui_from_vps_flag shall be equal to 0.”

The semantics for vui_parameters_present_flag may read as follows: “vui_parameters_present_flag equal to 1 specifies that the vui_parameters( )) syntax structure as specified in Annex E is present. vui_parameters_present_flag equal to 0 specifies that the vui_parameters( ) syntax structure as specified in Annex E is not present. When not present, the value of vui_parameters present_flag is inferred to be equal to 0.”

Other Considerations

Information and signals disclosed herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The techniques described herein may be implemented in hardware, software, firmware, or any combination thereof. Such techniques may be implemented in any of a variety of devices such as general purposes computers, wireless communication device handsets, or integrated circuit devices having multiple uses including application in wireless communication device handsets and other devices. Any features described as modules or components may be implemented together in an integrated logic device or separately as discrete but interoperable logic devices. If implemented in software, the techniques may be realized at least in part by a computer-readable data storage medium comprising program code including instructions that, when executed, performs one or more of the methods described above. The computer-readable data storage medium may form part of a computer program product, which may include packaging materials. The computer-readable medium may comprise memory or data storage media, such as random access memory (RAM) such as synchronous dynamic random access memory (SDRAM), read-only memory (ROM), non-volatile random access memory (NVRAM), electrically erasable programmable read-only memory (EEPROM), FLASH memory, magnetic or optical data storage media, and the like. The techniques additionally, or alternatively, may be realized at least in part by a computer-readable communication medium that carries or communicates program code in the form of instructions or data structures and that can be accessed, read, and/or executed by a computer, such as propagated signals or waves.

The program code may be executed by a processor, which may include one or more processors, such as one or more digital signal processors (DSPs), general purpose microprocessors, an application specific integrated circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Such a processor may be configured to perform any of the techniques described in this disclosure. A general purpose processor may be a microprocessor; but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Accordingly, the term “processor,” as used herein may refer to any of the foregoing structure, any combination of the foregoing structure, or any other structure or apparatus suitable for implementation of the techniques described herein. In addition, in some aspects, the functionality described herein may be provided within dedicated software modules or hardware modules configured for encoding and decoding, or incorporated in a combined video encoder-decoder (CODEC). Also, the techniques could be fully implemented in one or more circuits or logic elements.

The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs (e.g., a chip set). Various components, modules, or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily require realization by different hardware units. Rather, as described above, various units may be combined in a codec hardware unit or provided by a collection of inter-operative hardware units, including one or more processors as described above, in conjunction with suitable software and/or firmware.

Various embodiments of the invention have been described. These and other embodiments are within the scope of the following claims. 

What is claimed is:
 1. An apparatus configured to code video information, the apparatus comprising: a memory unit configured to store video information associated with a reference layer (RL) and an enhancement layer (EL), the RL having an RL picture in a first access unit, and the EL having a first EL picture in the first access unit, wherein the first EL picture is associated with a first set of parameters; and a processor in communication with the memory unit, the processor configured to: determine whether the first EL picture is an intra random access point (IRAP) picture; determine whether the first access unit immediately follows a splice point where first video information is joined with second video information including the first EL picture; and perform, based on the determination of whether the first EL picture is an intra random access point (IRAP) picture and whether the first access unit immediately follows a splice point, one of (1) refraining from associating the first EL picture with a second set of parameters that is different from the first set of parameters, or (2) associating the first EL picture with a second set of parameters that is different from the first set of parameters.
 2. The apparatus of claim 1, wherein the processor is further configured to perform at least one of (1) associating, based on a determination that the first EL picture is not an IRAP picture and that the first access unit does immediately follow a splice point, the first EL picture with the second set of parameters, or (2) refraining, based on a determination that the first EL picture is not an IRAP picture and that the first access unit does not immediately follow a splice point, from associating the first EL picture with the second set of parameters.
 3. The apparatus of claim 1, wherein the processor is configured to determine whether the first EL picture is an IRAP picture at least in part by: determining whether the first EL picture is indicated to be an IRAP picture; and determining whether a value of a flag or syntax element that is (1) included in a bitstream or (2) derived based on information included in the bitstream equals a predetermined value.
 4. The apparatus of claim 1, wherein the processor is configured to determine whether the first access unit immediately follows a splice point at least in part by determining whether a value of a flag or syntax element that is (1) included in a bitstream or (2) derived based on information included in the bitstream equals a predetermined value.
 5. The apparatus of claim 1, wherein the processor is further configured to: in response to determining that the first EL picture is not an IRAP picture and that the first access unit does not immediately follow a splice point, determine that a second access unit that follows the first access unit in coding order immediately follows a splice point, the second access unit including a second EL picture in the EL; and cause the EL to remain associated with the first set of parameters at least until the second EL picture is at least partially coded.
 6. The apparatus of claim 1, wherein the processor is further configured to: cause, based on a determination that the first EL picture is an IRAP picture, the first EL picture to be associated with the second set of parameters.
 7. The apparatus of claim 1, wherein the processor is configured to refrain from associating the first EL picture with the second set of parameters at least in part by: determining that a second EL picture in the EL that follows the first EL picture in coding order is an IRAP picture; and causing the EL to remain associated with the first set of parameters at least until the second EL picture is at least partially coded.
 8. The apparatus of claim 1, wherein the processor is configured to determine whether the first EL picture is an IRAP picture at least in part by processing header information associated with the first EL picture.
 9. The apparatus of claim 1, wherein the processor is configured to determine whether the first EL picture is an IRAP picture at least in part by processing a flag or a syntax element that indicates whether the first EL picture is an IRAP picture.
 10. The apparatus of claim 1, wherein the RL picture is associated with the first set of parameters, and wherein the processor is further configured to cause the RL to remain associated with the first set of parameters at least until a new coded video sequence is at least partially processed.
 11. The apparatus of claim 1, wherein the apparatus comprises at least one of an encoder or a decoder, and wherein the processor is further configured to at least one of encode or decode the video information in a bitstream.
 12. The apparatus of claim 1, wherein the apparatus comprises a device selected from a group consisting of one or more of: a computer, a notebook, a laptop computer, a tablet computer, a set-top box, a telephone handset, a smart phone, a smart pad, a television, a camera, a display device, a digital media player, a video gaming console, and an in-car computer.
 13. A method of encoding video information, the method comprising: determining whether a first enhancement layer (EL) picture in a first access unit of an EL is an intra random access point (IRAP) picture, the first EL picture associated with a first set of parameters; determining whether the first access unit immediately follows a splice point where first video information is joined with second video information including the first EL picture; and performing, based on the determination of whether the first EL picture is an intra random access point (IRAP) picture and whether the first access unit immediately follows a splice point, one of (1) refraining from associating the first EL picture with a second set of parameters that is different from the first set of parameters, or (2) associating the first EL picture with a second set of parameters that is different from the first set of parameters.
 14. The method of claim 13, further comprising one of (1) associating, based on a determination that the first EL picture is not an IRAP picture and that the first access unit does immediately follow a splice point, the first EL picture with the second set of parameters, or (2) refraining, based on a determination that the first EL picture is not an IRAP picture and that the first access unit does not immediately follow a splice point, from associating the first EL picture with the second set of parameters.
 15. The method of claim 13, wherein determining whether the first EL picture is an IRAP picture at least comprises: determining whether the first EL picture is indicated to be an IRAP picture; and determining whether a value of a flag or syntax element that is (1) included in a bitstream or (2) derived based on information included in the bitstream equals a predetermined value.
 16. The method of claim 13, wherein determining whether the first access unit immediately follows a splice point at least comprises determining whether a value of a flag or syntax element that is (1) included in a bitstream or (2) derived based on information included in the bitstream equals a predetermined value.
 17. The method of claim 13, further comprising: in response to determining that the first EL picture is not an IRAP picture and that the first access unit does not immediately follow a splice point, determining that a second access unit that follows the first access unit in coding order immediately follows a splice point, the second access unit including a second EL picture in the EL; and causing the EL to remain associated with the first set of parameters at least until the second EL picture is at least partially coded.
 18. The method of claim 13, further comprising causing, based on a determination that the first EL picture is an IRAP picture, the first EL picture to be associated with the second set of parameters.
 19. The method of claim 13, wherein refraining from associating the first EL picture with the second set of parameters at least comprises: determining that a second EL picture in the EL that follows the first EL picture in coding order is an IRAP picture; and causing the EL to remain associated with the first set of parameters at least until the second EL picture is at least partially coded.
 20. The method of claim 13, wherein determining whether the first EL picture is an IRAP picture at least comprises processing header information associated with the first EL picture.
 21. The method of claim 13, wherein determining whether the first EL picture is an IRAP picture at least comprises processing a flag or a syntax element that indicates whether the first EL picture is an IRAP picture.
 22. The method of claim 13, further comprising causing the RL that is associated with the first set of parameters to remain associated with the first set of parameters at least until a new coded video sequence is at least partially processed.
 23. A non-transitory computer readable medium comprising code that, when executed, causes an apparatus to perform a process comprising: storing video information associated with a reference layer (RL) and an enhancement layer (EL), the RL having an RL picture in a first access unit, and the EL having a first EL picture in the first access unit, wherein the first EL picture is associated with a first set of parameters; determining whether the first EL picture is an intra random access point (IRAP) picture; determining whether the first access unit immediately follows a splice point where first video information is joined with second video information including the first EL picture; and performing, based on the determination of whether the first EL picture is an intra random access point (IRAP) picture and whether the first access unit immediately follows a splice point, one of (1) refraining from associating the first EL picture with a second set of parameters that is different from the first set of parameters, or (2) associating the first EL picture with a second set of parameters that is different from the first set of parameters.
 24. The computer readable medium of claim 23, wherein the process further comprises one of (1) associating, based on a determination that the first EL picture is not an IRAP picture and that the first access unit does immediately follow a splice point, the first EL picture with the second set of parameters, or (2) refraining, based on a determination that the first EL picture is not an IRAP picture and that the first access unit does not immediately follow a splice point, from associating the first EL picture with the second set of parameters.
 25. The computer readable medium of claim 23, wherein the process further comprises: in response to determining that the first EL picture is not an IRAP picture and that the first access unit does not immediately follow a splice point, determining that a second access unit that follows the first access unit in coding order immediately follows a splice point, the second access unit including a second EL picture in the EL; and causing the EL to remain associated with the first set of parameters at least until the second EL picture is at least partially coded.
 26. A video coding device configured to code video information, the video coding device comprising: means for storing video information associated with a reference layer (RL) and an enhancement layer (EL), the RL having an RL picture in a first access unit, and the EL having a first EL picture in the first access unit, wherein the first EL picture is associated with a first set of parameters; means for determining whether the first EL picture is an intra random access point (IRAP) picture; means for determining whether the first access unit immediately follows a splice point where first video information is joined with second video information including the first EL picture; and means for performing, based on the determination of whether the first EL picture is an intra random access point (IRAP) picture and whether the first access unit immediately follows a splice point, one of (1) refraining from associating the first EL picture with a second set of parameters that is different from the first set of parameters, or (2) associating the first EL picture with a second set of parameters that is different from the first set of parameters.
 27. The video coding device of claim 26, further comprising one of (1) means for associating, based on a determination that the first EL picture is not an IRAP picture and that the first access unit does immediately follow a splice point, the first EL picture with the second set of parameters, or (2) means for refraining, based on a determination that the first EL picture is not an IRAP picture and that the first access unit does not immediately follow a splice point, from associating the first EL picture with the second set of parameters.
 28. The video coding device of claim 26, further comprising: means for determining, in response to determining that the first EL picture is not an IRAP picture and that the first access unit does not immediately follow a splice point, that a second access unit that follows the first access unit in coding order immediately follows a splice point, the second access unit including a second EL picture in the EL; and means for causing the EL to remain associated with the first set of parameters at least until the second EL picture is at least partially coded. 